These hardware threads share the entire memory hierarchy including L1. The programmer does not need to focus on the threading since the RTOS maps user software threads onto the processors hardware threads. To the programmer, these hardware threads can be considered as separate processor cores with shared memory, and are programmed using conventional software threading.

The initial Hexagon V1 core supported six threads, but the most recent version of Hexagon DSP, Hexagon V5 features three threads. The number of hardware threads has changed over the generations to meet various product and application needs. Implementations have evolved from simple Interleaved Multi-Threading (IMT) to more advanced prioritized scheduling to obtain the maximum efficiency to schedule as many execution slots as possible. Hexagon cores use a semi-custom physical design methodology with customizations oriented to power reductionĪll versions of the Hexagon DSP core are hardware multi-threaded to enable superior concurrency needed in mobile applications. Through carefully orchestrated hierarchical clock gating, near perfect power scaling is achieved. One of the challenges with multi-threading is to have the power scale with the number of threads running. Keeping the speed targets low allows the implementation to avoid many of the power-costly design methods that are typical of high speed design. Rather than pushing performance through MHz, the designs strive for high levels of work per cycle, but at a reduced clock speed. Energy efficiency is often the more critical metric. Hexagon cores are optimized for both high performance and energy efficiency. At Uplinq 2013, we released the first publicly available development environment for the Hexagon DSP, the Hexagon SDK. The “Hexagon DSP” core is now in its 5th generation and is integrated inside all recent Qualcomm Technologies modem and application chips. As of 2012, multiple Hexagon cores form the processing engine behind virtually every commercially shipping 4G LTE modem by Qualcomm Technologies.

In 2011 the Hexagon Access program was started to allow customers to program the DSP and thus exploit the power & performance benefits of offloading the ARM cores for performance, reduced power dissipation, or concurrency requirements. Qualcomm Technologies began development of a new DSP processor architecture and high-performance implementation in the Fall of 2004.

Technical hexagon